The present invention relates to a semiconductor device and a manufacturing method therefor.
Requirement of further high integration and high speed has been increased in manufacturing technology in a field of integrated circuits of the electronics industry. In addition, scale of the circuit has become large and difficulty in its design has been increased because of progress of integration.
An integration circuit mounting a logic circuit and a memory circuit over the same semiconductor substrate, what is called a circuit mounted in a mixed manner has following characteristics. Integration can be increased because the logic circuit and the memory circuit exist over the same substrate. Not only that, but also increase in operation speed is also possible because wiring between the circuits becomes short.
However, when a memory circuit including a capacitance element and a logic circuit are mounted over the same semiconductor substrate, a structure that is not used when a common logic circuit is formed is required to be used in order to form the capacitance element used for storage of data that the memory circuit has. For example, in a trench type capacitance element, a method in which a deep groove having a depth of several microns in the semiconductor substrate is formed and a capacitance element is formed therein is reported. However, a diameter of a trench opening becomes small with more microscopic formation of the element. Not only that, but also the depth becomes deeper and deeper in order to secure the capacity. Difficulty in manufacturing process of the trench type capacitance element is significantly increased.
On the other hand, in a stack type capacitance element, a fin type and a cylinder type stack structure are employed in order to realize desired capacity. What is called a COB structure (a Capacitor Over Bit line structure) is a structure in which a capacitance element is formed over a bit line. In the COB structure, height of the capacitor is set high in order to gain a capacity of the capacitance element. For example, in FIG. 22 of Patent Document 1, a stack type capacitance element which is formed in the same layer as a contact insulating layer is described as a related art. In this stack type structure, to gain height of a capacitance element 430 means that distance between a wiring of a lower part of the capacitance element and wiring of an upper part of the capacitance element becomes far. Thereby, in a logic circuit part, a contact 420b located in the same layer as the capacitance element from a first wiring layer to a diffusion layer also becomes high. In the manufacturing process, difficulty of the manufacturing process is increased. Not only that, but also parasitic resistance and parasitic capacity are increased.
When the memory circuit and the logic circuit are formed over the same semiconductor substrate, design which considers increased parasitic resistance and parasitic capacity of the contact caused by forming the capacitance element should be done, when the logic circuit is designed. This means that, even when the same logic circuit is designed, design parameters may be required be changed whether the capacitance element exists over the same semiconductor substrate or not. Despite the completely same circuit, the design should be done again because the circuit and the capacitance element are formed at the same time. Not only that, but also by mounting the capacitance element in a mixed manner, the circuits may decrease its operation speed, may not be operated due to decrease in its operating margin, or may increase its power consumption. For example, in FIG. 22 of Patent Document 1, when height of the capacitance element 430 is set high in order to increase capacity, height of the contact 420b also becomes high at the same time. As a result, operation speed of the logic circuit is contrarily decreased in the logic circuit.
Patent Document 1 describes a structure of a semiconductor device in which the height of the contact 420b of the logic circuit part is decreased. In Patent Document 1, in a related art, a capacitor plate and an interlayer insulating film and a capacitor contact are stacked in this order from the capacitance element to an upper part capacitor wiring. However, in an integrated circuit device 100 of the embodiment, the upper part capacitor wiring 122a is directly stacked over the upper surface of the capacitance element 130. Consequently, in the integrated circuit device 100 of the embodiment, a thickness between the upper surface and the lower surface of a logic contact 119 becomes thin by a thickness between the upper surface and the lower surface of the sum of the capacitor plate, the interlayer insulating film and a capacitor contact of the related art. Accordingly, it is described that, in the integrated circuit device 100 of the embodiment, an aspect ratio of the logic contact 119 can be decreased, and a thickness between the upper surface and the lower surface of the capacitance element 130 can be secured at the same time (FIG. 11).
In Patent Document 2, a capacitance element is embedded in a memory circuit part. On the other hand, in a logic circuit part located in the same layer as the capacitance element, a first layer wiring 200 is formed between a contact plug 33 and an upper part wiring film 202. Patent Document 2 describes that the height of the logic contact in the logic circuit part can be decreased compared with the related art by forming this first layer wiring 200 in an intermediate part of the capacitance element 44 (FIG. 7).
[Patent Document 1]
Japanese Unexamined Patent Application Publication No. 2007-201101
[Patent Document 2]
Japanese Unexamined Patent Application Publication No. 2004-342787
[Patent Document 3]
International Publication No. WO 97/19468 Pamphlet
[Patent Document 4]
Japanese Unexamined Patent Application Publication No. 2007-67451
[Non-patent Document 1]
International Electron Device Meeting Digest of Technical Papers IEEE, pp. 619-622, 2008